CS ChipSettle EU chip-design settlement
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Spain

CIT ~25% Pillar Two ✓

25% headline rate. PERTE Chip is the largest national semiconductor funding envelope in the EU by announced volume and includes a dedicated design pillar; execution has been slower than announced.

✓ 3 Jul 2026

Instruments (4)

FDI screening & export control

⚠ Semiconductors in scope
Threshold
10% of share capital or effective management control, for a non-Spanish investor into a sensitive-sector target; temporarily extended to EU/EFTA investors for deals >€500M or listed targets through end of 2026
Authority
Consejo de Ministros, via the Dirección General de Comercio Internacional e Inversiones
Timeline
Several months for a full authorization; can extend materially for complex/contested cases

Semiconductors are explicitly listed among the critical technologies and dual-use products covered. As elsewhere, the regime is built around acquiring a stake/control in an existing Spanish target — a new subsidiary formed from scratch is generally not itself the trigger, but any acquisition, JV, or asset deal involving Spanish semiconductor capability should be checked against current guidance.

Legal basis: Law 19/2003, Art. 7 bis; Royal Decree 571/2023; extended by Real Decreto-ley 1/2025 — source ↗ ✓ 3 Jul 2026

Labor law snapshot

Works council
Comité de empresa mandatory at 50+ employees; delegados de personal (staff delegates) for 6–49
Notice periods
Statutory minimum 15 calendar days (Estatuto de los Trabajadores), but 86.7% of the workforce is covered by a convenio colectivo that often extends this to 30 days–3 months
Bargaining
Very influential — sector convenios colectivos largely set salary grids and conditions; statutory severance is 20 days' salary/year (objective dismissal, capped at 12 months) or 33 days/year (unfair dismissal, capped at 24 months)

✓ 3 Jul 2026 · orientation only, verify with local counsel

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